Unified (A)Synchronous Circuit Development

Unified (A)Synchronous Circuit Development

Abstract

Despite its development several decades ago and several very beneficial properties asynchronous logic design, which is data driven and runs as fast as possible in all situations, is rarely used nowadays. Reasons are of course its disadvantageous properties such as bad testability but also required sophisticated knowledge for designers and missing tools. In this paper we draw a path to tackle the latter points by suggesting a tool/way to generate multiple circuit implementations from a single description. We are aiming to convert specifications written in various input languages, e.g. C or VHDL, to an unified Internal Representation (IR). This IR is composed of building blocks (semantic vocabulary) specified through the Abstract State Machine (ASM) based formal method. The ASM artifact is then used to generate the circuit in the desired (a)synchronous design style. As short term goal we aim to train developers by reading synchronous descriptions and converting them to asynchronous designs however in the long run we hope to establish a unified path for circuit development, which only requires an abstract behavioral description.

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Authors
  • Paulweber, Philipp
  • Maier, Jürgen
  • Cortadella, Jordi
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Shortfacts
Category
Paper in Conference Proceedings or in Workshop Proceedings (Paper)
Event Title
25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
Divisions
Software Architecture
Subjects
Programmiersprachen
Angewandte Informatik
Theoretische Informatik
Event Location
Hirosaki, Japan
Event Type
Conference
Event Dates
12-15 May 2019
Date
12 May 2019
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